1. Field of the Invention
The present invention generally relates to amplifiers. More specifically, the present invention provides significant gain enhancement while minimizing noise introduction for differential amplifiers using cascode structures.
2. Background Art
Differential amplifiers are designed generally to amplify input signals while minimizing noise introduction and signal distortion. Conventional differential amplifiers are designed often using larger-sized transistors to boost gain and lower noise but at the expense of introducing higher levels of parasitic capacitance. Alternatively, conventional differential amplifiers can use smaller-sized transistors that provide less gain to maintain signal integrity. However, to provide required gain levels, conventional differential amplifiers that use smaller-sized transistors often require multiple gain stages and therefore additional circuit elements which increases design complexity and costs.
FIG. 1 illustrates a conventional differential amplifier with a cascode stage 100. The conventional differential amplifier 100 includes differential transistor pair 102 and 104 and cascode transistor pair 106 and 108. Transistor 102 is coupled to a first component of a differential input 110. The first component of differential input 110 receives a first component of a differential input signal (labeled as “IN-i” in FIG. 1). The first component of the differential input signal can be, for example, a first component of a differential input voltage. Transistor 104 is coupled to a second component of a differential input 112. The second component of differential input 112 receives a second component of a differential input signal (labeled as “IN-n” in FIG. 1). The second component of the differential input signal can be, for example, a second component of a differential input voltage. As further shown in FIG. 1, the differential transistor pair 102 and 104 is coupled to a bias current source 114.
The cascade transistor pair 106 and 108 is coupled to the differential transistor pair 102 and 104 to increase the gain of the conventional differential amplifier 100. Transistor 106 is coupled to a biasing source (labeled for simplicity as “BIAS” in FIG. 1). The biasing source can be, for example, a bias voltage supply. Transistor 106 is coupled to a first component of a differential output 116. The first component of differential output 116 provides a first component of a differential output signal (labeled as “OUT-n” in FIG. 1). The first component of the differential output signal can be, for example, a first component of a differential output voltage. Transistor 108 is also coupled to a biasing source (labeled for simplicity as “BIAS” in FIG. 1). The biasing source can be, for example, a bias voltage supply. Transistor 108 is coupled to a second component of a differential output 118. The second component of differential output 118 provides a second component of a differential output signal (labeled for simplicity as “OUT-i” in FIG. 1). The second component of the differential output signal can be, for example, a second component of a differential output voltage.
The conventional differential amplifier 100 is coupled to a second stage amplifier (not shown in FIG. 1). The goal of the conventional differential amplifier 100 is to amplify a differential input 110, 112 to provide an amplified differential output 116, 118 while minimizing the amount of noise and signal distortion introduced during amplification. Larger-sized transistors generally provide higher gain but at the expense of introducing more noise into the amplified signal. Smaller-sized transistors generally introduce less relative noise but at the expense of lower gain.
As the size of a CMOS transistor is decreased, the intrinsic gain of the CMOS transistor—defined as the change in drain voltage for a change in gate voltage (or source voltage)—also decreases. The intrinsic gain can generally be considered to be the ratio of RDS to 1/gm of the CMOS transistor, where RDS is the drain-to-source resistance and gm is the transconductance of the CMOS transistor.
For a CMOS transistor fabricated in a 65 nm process, the intrinsic gain of the CMOS transistor is approximately 5 to 7. Using CMOS transistors of this scale in the conventional differential amplifier 100, the gain of the differential transistor pair 102, 104 is approximately 5 to 7, the gain of the cascade transistor pair 106, 108 is also approximately 5 to 7, and the overall gain of the conventional differential amplifier is approximately 25 to 49. While CMOS transistors at the 65 nm node generally provide greater bandwidth, the overall gain of the conventional differential amplifier 100 is generally too low for many applications when such transistors are used. Using larger-sized CMOS transistors to boost the overall gain of the conventional differential amplifier 100, however, introduces too much parasitic capacitance for many applications. The design of the conventional differential amplifier 100 may therefore be deficient in terms of overall gain when, for example, CMOS transistors fabricated in a 65 nm process, or even larger transistors, are employed.
Accordingly, what is needed is a differential amplifier design that can provide high levels of gain using low noise transistors without requiring multiple gain stages.